The present invention relates to semiconductor devices, and more particularly to a semiconductor integrated circuit which includes a multiplicity of CMIS (complementary metal-insulator-semiconductor) transistors each made up of a first MISFET (metal-insulator-semiconductor field effect transistor) of a first conductivity type and a second MISFET of a second conductivity type. In more detail, the present invention relates to a semiconductor memory device suited to be used as a static random access memory which is high in packing density and low in stand-by power.
In a conventional static random access memory cell of the CMIS type, as shown in FIG. 12, two N-channel drive MISFET's T.sub.1 and T.sub.2 and two P-channel load MISFET's T.sub.3 and T.sub.4 are connected so as to form two inverter circuits, which are coupled with each other in cross connection to form a flip-flop circuit. Further, N-channel transfer MISFET's T.sub.5 and T.sub.6 are connected to storage nodes N.sub.1 and N.sub.2 of the flip-flop circuit, respectively. One and the other ends of the flip-flop circuit are applied with a power supply voltage V.sub.CC and a ground potential, respectively. Data lines 6 and 6' are connected to the drains of the transfer MISFET's T.sub.5 and T.sub.6, respectively, and the common gate line of the transfer MISFET's T.sub.5 and T.sub.6 is used as a word line 3. As is well known, such a static random access memory cell is operated in the following manner. That is, the word line 3 is activated to store a logical value "1" or "0" (that is, high or low logical value) in a storage node N.sub.1 or N.sub.2, or to read out the state of the storage node. The static random access memory cell provided with such a CMIS circuit has a feature that only the leakage current of MISFET is generated in a stand-by period, and thus stand-by power is small.
A semiconductor memory device having the above memory cell at a high packing density is described in, for example, an article entitled "Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon" (IEEE, Trans. Electron Devices, Vol. ED-32, No. 2, 1985, pages 258 to 281). In this semiconductor memory device, the P-channel load MOSFET's (metal-oxide-semiconductor field effect transistors) of the flip-flop circuit are formed in such a manner that a polycrystalline silicon film for the load MOSFET's is piled on the N-channel drive MOSFET's of the flip-flop circuit. FIGS. 10 and 11 are plan and sectional views showing a static random access memory cell which is described in the above-referred article, respectively. That is, FIG. 11 is a sectional view taken along the line XI--XI of FIG. 10. Referring to FIGS. 10 and 11, at least the upper and side surfaces of the gate electrode 4b of an N-channel drive MOSFET formed in a silicon substrate are coated with a thin silicon oxide film 13, and a polycrystalline silicon film is formed on the silicon oxide film 13. The source region 5c, drain region 5b and channel region 5e of a P-channel load MOSFET are formed in the polycrystalline silicon film. The channel region 5e is formed so that the gate electrode 4b of the N-channel drive MOSFET is placed under the channel region 5e. Thus, the gate electrode 4b of the N-channel drive MOSFET can also be used as the gate electrode of the P-channel load MOSFET, and the silicon oxide film 13 is used as the gate insulating film of the P-channel load MOSFET. In more detail, the drive MOSFET's of the flip-flop circuit are made up of an N-type region 1e for forming a common source region, N-type regions 1c and 1d for forming drain regions, and gate electrodes 4b and 4c. The gate electrodes 4b and 4c are connected to the N-type regions 1c and 1d through contact holes 2a and 2b, respectively. Further, the N-type regions 1c and 1d for forming the drain regions of the drive MOSFET's are also used as the source regions of the N-channel transfer MOSFET's connected to the flip-flip circuit, and thus are used as the storage nodes of the flip-flop circuit. The N-channel transfer MOSFET's are made up of the N-type regions 1c and 1d for forming the source regions, a common gate electrode 4a, and N-type regions la and 1b for forming drain regions. The N-type regions 1a and 1b are connected to aluminum electrodes 8a and 8b through contact holes 7a and 7b, respectively. The common gate electrode 4a is used as a word line, and the aluminum electrodes 8a and 8b are used as data lines. Further, a contact hole 7c is provided on the drain region 5a of one P-channel load MOSFET and the gate electrode 4b of one N-channel drive MOSFET so that the drain region 5a and the gate electrode 4b are both exposed, and the drain region 5a is connected to the gate electrode 4b through an aluminum electrode 8c fulling up the contact hole 7c. Similarly, another contact hole 7d is provided on the drain region 5b of the other P-channel load MOSFET and the gate electrode 4c of the N-channel drive MOSFET so that the drain region 5b and the gate electrode 4c are both exposed, and the drain region 5b is connected to the gate electrode 4c through an aluminum electrode 8d filling up the contact hole 7d. It is to be noted that the drain regions 5a and 5b of the P-channel load MOSFET's are formed of a low-resistive polycrystalline silicon film which is heavily doped with a P-type impurity. Further, the common source region 5c of the P-channel load MOSFET's is formed of the low-resistive polycrystalline silicon film which is heavily doped with the P-type impurity, and is applied with a power supply voltage V.sub.cc. The channel regions 5d and 5e of the P-channel load MOSFET's are placed over the gate electrodes 4c and 4b, respectively.